Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOS transistor is increased and as manufacturing costs are reduced.
A typical MOS semiconductor device includes a semiconductor substrate on which a gate electrode is disposed. The gate electrode, which acts as a conductor, is separated from the substrate by an insulating layer typically made from a gate oxide film, such as silicon oxide (SiO2). Source and drain regions are typically formed in regions of the substrate adjacent the gate electrode by doping the regions with a dopant of a desired conductivity. The insulating layer is provided to prevent current from flowing between the gate electrode and the source, or drain regions.
In operation, a voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electric field is set up in the channel region below the gate oxide and between the source and drain regions. By varying the transverse electric field, it is possible to modulate the conductance of the channel region between the source and drain regions. In this manner an electric field is used to control the current flow through the channel region.
One specific type of MOS semiconductor device is a nonvolatile memory device such as a flash EEPROM (electrical erasable programmable read only memory device). FIG. 1 represents the relevant portions of a typical flash memory device 10. The memory cell 10 typically includes a source region 12, a drain region 14 and a channel region 16 in a substrate 18; and a stacked gate structure 20 overlying the channel region 16. The stacked gate 20 includes a thin gate dielectric layer 22 (commonly referred to as the tunnel oxide) formed on the surface of the substrate 18. The stacked gate 20 also includes a polysilicon floating gate 24 which overlies the tunnel oxide 22 and an interpoly dielectric layer 26 which overlies the floating gate 24. The interpoly dielectric layer 26 is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers 26a and 26b sandwiching a nitride layer 26c. Lastly, a polysilicon control gate 28 overlies the interpoly dielectric layer 26. The channel region 16 of the memory cell 10 conducts current between the source region 12 and the drain region 14 in accordance with an electric field developed in the channel region 16 by the stacked gate structure 20.
Generally speaking, a flash memory device is programmed by inducing hot electron injection from a portion of the substrate, such as the channel section near the drain region, to the floating gate. Electron injection carries negative charge into the floating gate. The injection mechanism can be induced by grounding the source region and a bulk portion of the substrate and applying a relatively high positive voltage to the control electrode to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain region in order to generate “hot” (high energy) electrons. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage (Vth) of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent “read” mode. The magnitude of the read current is used to determine whether or not a flash memory device is programmed. The act of discharging the floating gate of a flash memory device is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source region and a 0V to the control gate and the substrate while floating the drain of the respective memory cell.
Referring again to FIG. 1, conventional source erase operations for the flash memory device 10 operate in the following manner. The memory cell 10 is programmed by applying a relatively high voltage VG (e.g., approximately 12 volts) to the control gate 28 and a moderately high voltage VD (e.g., approximately 9 volts) to the drain region 14 in order to produce “hot” electrons in the channel region 16 near the drain region 14. The hot electrons accelerate across the tunnel oxide 22 and into the floating gate 24 and become trapped in the floating gate 24 since the floating gate 24 is surrounded by insulators (the interpoly dielectric 26 and the tunnel oxide 22). As a result of the trapped electrons, the threshold voltage of the memory cell 10 increases by about 3 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the memory cell 10 created by the trapped electrons causes the cell to be programmed.
To read the flash memory device 10, a predetermined voltage VG that is greater than the threshold voltage of an unprogrammed cell, but less than the threshold voltage of a programmed cell, is applied to the control gate 28. If the memory cell 10 conducts, then the memory cell 10 has not been programmed (the cell 10 is therefore at a first logic state, e.g., a zero “0”). Likewise, if the memory cell 10 does not conduct, then the memory cell 10 has been programmed (the cell 10 is therefore at a second logic state, e.g., a one “1”). Consequently, it is possible to read each cell 10 to determine whether or not it has been programmed (and therefore identify its logic state).
In order to erase the flash memory device 10, a relatively high voltage VS (e.g., approximately 12 volts) is applied to the source region 12 and the control gate 28 is held at a ground potential (VG=0), while the drain region 14 is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide 22 between the floating gate 24 and the source region 12. The electrons that are trapped in the floating gate 24 flow toward and cluster at the portion of the floating gate 24 overlying the source region 12 and are extracted from the floating gate 24 and into the source region 12 by way of Fowler-Nordheim tunneling through the tunnel oxide 22. Consequently, as the electrons are removed from the floating gate 24, the memory cell 10 is erased.
The ONO interpoly dielectric layer has a number of important functions including insulating the control gate from the floating gate. Accordingly, it is desirable to form a high quality ONO interpoly dielectric layer. When forming an ONO interpoly dielectric layer, there are a number of concerns. For example, if the top oxide layer is too thick, the required programming voltage increases undesirably. On the other hand, if the top oxide layer is too thin (for example, less than 10 Å), charge retention time decreases undesirably since the charge tends to leak. Moreover, if the nitride layer is too thin, charge leakage from the floating gate to the control gate may be caused, further decreasing charge retention time. Precisely controlling the properties of the ONO interpoly dielectric layer such as thickness of the layers is important, therefore, in controlling the quality and the reliability of the resulting memory device.
It may also be desirable to utilize high-k (high dielectric constant) dielectric materials in ONO interpoly dielectric layers of memory devices. Since 1994, the International Technology Roadmap for Semiconductors (ITRS) has recommended a steady reduction in silicon device size, with an accompanying improvement in device performance, measured predominantly by circuit speed. The ITRS has served as a sort of “how-to” guide for the preservation of Moore's Law, the time-honored pronouncement of these ever-increasing component densities. While a variety of new materials and processes have been added to silicon process technology to maintain this rate of device scaling, a primary limitation has been in the area of photolithography and the ability to pattern and etch the ever-smaller device features. Recently, however, it has become clear that this steady scaling of feature sizes may be limited by the thickness of oxide films made of silicon dioxide (SiO2). This impending barrier has led to the development of new dielectrics as potential replacements for SiO2, known collectively as high-k dielectrics that do not limit the thickness of oxide films. Examples of possible high-k gate oxide materials include silicon nitride (Si3N4), silicon oxynitrides (SixNyOz), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum pentoxide (Ta2O5), hafnium oxide (HfO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate (SrTiO3) and barium strontium titanate (BaSrTiO3), barium titanate (BaTiO3), titanium dioxide (TiO2), cerium oxide (CeO2), lead titanate (PbTiO3), lead zirconate (PbZrO3), tungsten oxide (WO3), barium strontium titanate (BST) (Ba1-x,Srx,TiO3), PMN (PbMgxNb1-xO3), PZT(PbZrxTi1-xO3), PZN (PbZnxNb1-xO3), and PST (PbScxTa1-xO3), and silicates and aluminates of these oxides.
In any event, the formation of the high-k oxide films in ONO interpoly dielectric layers of memory devices is also important to the quality and the reliability of the finished memory device. In particular, it is important to obtain high-k oxide films that have a uniform thickness and a controlled microstructure so that resulting ONO interpoly dielectric layers exhibit less charge leakage and increased reliability.
What is desired are improved methods of forming ONO interpoly dielectric layers of memory devices. What is also desired are improved methods of forming ONO interpoly dielectric layers using high-k materials. Preferably, the resulting memory devices will exhibit less charge leakage and increased reliability.